Search - fir vhdl

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[VHDL-FPGA-Verilog] coeff_rom_2_5

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

Description: 扩频发射机，信道编码采用(2, 1, 7)卷积码, 扩频模块采用扩频长度255 的kasami码, 极性变换模块为3bit 量化模式, 内插模块为每两比特间插入7bit 和输出滤波为16 阶的FIR 滤波器。-direct sequence spread spectrum transmitter
Platform: | Size: 1024 | Author: 靳超 | Hits:

[Other] fir_16

Description: vhdl代码实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
Platform: | Size: 3072 | Author: sumli | Hits:

[SCM] case4

Description: DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter
Platform: | Size: 10240 | Author: 黄萌 | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] FirFilter

Description: 对称型线性相位FIR滤波器的VHDL源程序，比直接型FIR滤波器速度快一半-VHDLSourceProgramofFirFilter
Platform: | Size: 1024 | Author: 杨波 | Hits:

[VHDL-FPGA-Verilog] 3

Description: FIR数字滤波器的优化与验证 -FIR digital filter optimization and verification FIR digital filter optimization and verification
Platform: | Size: 336896 | Author: 南才北往 | Hits:

[DSP program] fri

Description: 滤波器的设计的，用于FIR滤波器的设计和应用-The design of filters for the FIR filter design and application
Platform: | Size: 650240 | Author: qian | Hits:

[DSP program] FIR

Description: 详细的介绍的通过DSP编写滤波器的过程，图形并茂，非常好的资料，希望与大家共享，共同进步,超棒的资料-Detail the preparation of the filter through the process of DSP, graphics and Mao, very good information, I hope to share with you and common progress, great information
Platform: | Size: 247808 | Author: 爷们 | Hits:

[VHDL-FPGA-Verilog] filter_vhdl

Description: vhdl语言编写的fir和iir滤波器程序。在quartus上仿真通过。-vhdl language program fir and iir filters. Quartus adopted in the simulation.
Platform: | Size: 37888 | Author: lmy | Hits:

[VHDL-FPGA-Verilog] fir_hdl

Description: 一个 FIR 滤波器的 verilog 实现，与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Platform: | Size: 97280 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Platform: | Size: 1024 | Author: onion | Hits:

[ARM-PowerPC-ColdFire-MIPS] VHDL_100_1

Description: 第43例四位移位寄存器第44例寄存／计数器第45例顺序过程调用第46例 VHDL中generic缺省值的使用第47例无输入元件的模拟第48例测试激励向量的编写第49例 delta延迟例释第50例惯性延迟分析第51例传输延迟驱动优先第52例多倍（次）分频器第53例三位计数器与测试平台第54例分秒计数显示器的行为描述6 第55例地址计数器第56例指令预读计数器第57例加.c减.c乘指令的译码和操作第58例 2－4译码器结构描述第59例 2－4译码器行为描述第60例转换函数在元件例示中的应用第61例基于同一基类型的两分辨类型的赋值相容问题第62例最大公约数的计算第63例最大公约数七段显示器编码第64例交通灯控制器第65例空调系统有限状态自动机第66例 FIR滤波器第67例五阶椭圆滤波器第68例闹钟系统的控制第69例闹钟系统的译码第70例闹钟系统的移位寄存器第71例闹钟系统的闹钟寄存器和时间计数器第72例闹钟系统的显示驱动器
Platform: | Size: 340992 | Author: zyw | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list